This invention relates, in general, to transmitter/receiver circuits, and more particularly to transmitter/receiver circuits for interfacing digital circuits having logic levels of two different voltage ranges.
System designs based on multiple interconnected integrated circuits are achieving extremely high system speeds. Higher transistor densities, increased functionality on a chip, increased levels of interconnect, and packaging advances are but a few of the areas where significant gains have been made to enhance system performance. Integrated circuit system speeds are often limited by a particular class of circuits or an individual circuit which must drive a highly capacitive or inductive load. The circuit or circuits limiting system speed can be anywhere on the integrated circuit. One class of circuits which are notorious for limiting system speed are input/output circuits or I/O circuits. Input/output circuits are the external interface of the integrated circuit and often must drive highly inductive or capacitive loads. Transmission line effects can also affect signal quality if the I/O circuits transfer data at high speeds. For example, a digital system comprising multiple CMOS integrated circuits can be limited in system speed by the ability of each integrated circuit to transfer information between each other. CMOS integrated circuits commonly operate at 5 volts. A one logic level is approximately 5 volts and a zero logic level is approximately zero volts in a five volt system. A CMOS interface circuit is limited in drive strength due to the performance characteristics of a CMOS device and size limitations of an input/output site (where the interface circuitry is placed). Large capacitive and inductive loading on the interface circuit and "rail to rail" (zero to five volt) signal swings limit the speed in which information can be transferred.
A universal approach used throughout the industry to achieve higher transfer speeds is to reduce signal swing levels. The concept is extremely simple, it takes less time to generate a small voltage change than it does to generate a large voltage change for a given loading. For bipolar circuits, Emitter Coupled Logic (ECL) is a common approach, for CMOS circuits, Gunning Transceiver Logic (GTL) is extensively used. Although speed is gained by using small signal levels there are disadvantages. A few of the disadvantages are reduced noise margins, increased circuit complexity, and increased D.C. power dissipation. Also, circuitry internal to the integrated circuit, is typically responsive to digital signals having logic levels of a larger voltage range, thus the small signal levels at the interface must be translated to the internal logic levels.
Of particular interest is Gunning Tranceiver Logic (GTL), this is made more so by the increased demand and usage of CMOS circuitry for high performance integrated circuit systems. GTL is an interface approach well known by those skilled in the art. Two distinct circuits are used in GTL, they are a transmitting circuit and a receiving circuit. An input/output cell of an integrated circuit must have both types of circuits if it is to receive and transmit data. Signal levels used in GTL are Voh.about.1.2 volts (one logic state) and Vol.about.0.4 volts (zero logic state). A load resistor or pull up resistor is coupled to a 1.2 volt voltage reference and a signal line. A single resistor or multiple load resistors are used depending on the configuration, the load resistor also acts as a termination to reduce reflections. A GTL transmitter circuit is an open drain n-channel CMOS transistor coupled to the signal line for generating a zero logic state on the signal line. The load resistor generates a one logic state on the signal line when all transmitter circuits are disabled. A GTL receiver circuit is a comparator with an input coupled to a 0.8 volt voltage reference and a second input coupled to the signal line. The receiver circuit receives a one or zero logic state from the signal line and outputs a corresponding one or zero logic state at the internal integrated circuit logic levels.
Reducing signal swings to 800 millivolts not only increases speeds at which data can be transferred within a system but reduces crosstalk between signal lines and reduces power dissipation. GTL circuitry can be fabricated using devices standard to a CMOS process flow. The load resistor or pull-up resistor which also acts as a termination resistor can be fabricated on chip or added on as an external component. Although GTL solves many of the problems for increasing system performance it also has some negative features. First, GTL is not directly compatible with ECL interface logic, thus it does not lend itself to mixed use (ECL and GTL circuits in the same system). Second, GTL requires a stable 0.8 voltage reference which adds circuitry (and complexity) to the interface logic. Third, a stable 1.2 volt power supply must be added which can handle large transient currents. Fourth, GTL is difficult to design for differential coupling which is essential to decrease noise through common mode rejection. Fifth, the speed at which a one logic level is generated is limited by the value of the termination resistor. Sixth, power dissipation can be a problem when hundreds of transmitter/receiver circuits are used on a integrated circuit. The current to generate a zero logic level is not insignificant. Finally, the industry is moving to lower power supply voltages for CMOS circuitry from 5 volts to 3 volts, the open drain n-channel devices used in GTL to generate a zero logic level will have to drastically increase in size to maintain speeds at the lower voltages.
It would be of great benefit if a digital logic transmitter/receiver circuitry could be developed which is compatible with ECL logic levels, eliminate the need for secondary power supply voltage levels or reference voltages, reduce the need for termination resistors, have both single ended and differential drive, is functional at 5 volts or 3 volts, and is compatible with multiple technologies (CMOS, Bipolar, etc.).